NAND basic cell using structural vhdl -

i have problem designing memory circuits in vhdl. trying figure out soultion following prompt:

create nand basic cell in xilinx tools using structural vhdl methods. add 1ns gate delay both nand gates (for both rising , falling transitions). label inputs s , r , outputs q , qn appropriate. create vhdl test bench simulate circuit, driving inputs specified below.

de-assert both inputs @ start of simulation. @ 100ns, asset s. @ 200ns, de-assert s. @ 300ns, assert r. @ 400ns, de-assert r. @ 500ns, assert both inputs. @ 600ns, de-assert both inputs. @ 700ns, assert both inputs.

1. an undefined output
2. a set operation
3. a reset operation
4. a ‘0’ being stored in memory
5. a ‘1’ being stored in memory
6. a state q , qn outputs both driven same value
7. a metastable state

if basic example of code can design nor circuit (that actual problem wish solve) nand example sufficient.

i have tried using model structural code

 import std_logic ieee library     library ieee;     use ieee.std_logic_1164.all;      --entity declaration: name, inputs, outputs     entity nandgate        port( a, b : in std_logic;                 f : out std_logic);     end nandgate;      --functional description: how nand gate works     architecture func of nandgate      begin        f <= nand b;     end func;  , model test bench      architecture tb of nandgate_tb        --pass nandgate entity testbench component         component nandgate        port( a, b : in std_logic;                 f : out std_logic);        end component;         signal  ina, inb, outf : std_logic;     begin        --map testbench signals ports of nandgate        mapping: nandgate port map(ina, inb, outf);         process           --variable track errors           variable errcnt : integer := 0;        begin           --test 1           ina <= '0';           inb <= '0';           wait 15 ns;           assert(outf = '1')  report "error 1" severity error;           if(outf /= '1')              errcnt := errcnt + 1;           end if;            --test 2           ina <= '0';           inb <= '1';           wait 15 ns;           assert(outf = '1')  report "error 2" severity error;           if(outf /= '1')              errcnt := errcnt + 1;           end if;            --test 3           ina <= '1';           inb <= '1';           wait 15 ns;           assert(outf = '0')  report "error 3" severity error;           if(outf /= '0')              errcnt := errcnt + 1;           end if;            -------------- summary -------------           if(errcnt = 0)              assert false report "good!"  severity note;           else              assert true report "error!"  severity error;           end if;         end process;     end tb; 

the question asking create sr latch (called nand basic cell in instructions) cross-coupled pair of nand gates. delay mentioned in logic equation functional description of nand gate.

the following structural vhdl model of sr latch made of 2 nand gates:

entity nandcell    port( s, r  : in std_logic; --s , r active low          q, qn : out std_logic); end nandcell;  architecture structural of nandcell     --nand gate component declaration    signal qint, qnint : std_logic; --these internal signals required able read "outputs" begin    n1 : nandgate port map(s, qnint, qint);    n2 : nandgate port map(r, qint, qnint);    q <= qint;    qn <= qnint; end structural;