How to create 2's Complement Adder in Verilog? -


this ripple carry adder being used, however, when sub = 1 = 4 b = 3, program returning no overflow , sum 1100 instead of 0110. have messed carry behavior?

module fulladder(a, b, cin, sum, cout);     input a, b, cin;     output sum, cout;     assign sum = a^b^cin;     assign cout = (cin&a) | (cin&b) |(a&b); endmodule   module rca4bit(a, b, c0, sum, c1, overflow);     input [3:0] a;     input [3:0] b;     output [3:0] sum;     input c0;     output c1;     output overflow;      wire [2:0] carry;      fulladder rca1(a[0], b[0], c0, sum[0], carry[0]);      fulladder rca2(a[1], b[1], carry[0], sum[1], carry[1]);      fulladder rca3(a[2], b[2], carry[1], sum[2], carry[2]);      fulladder rca4(a[3], b[3], carry[2], sum[3], c1);      assign overflow = c1 ^ carry[2]; endmodule  module rca4bit2cmp(a, b, sub, sum, c1, overflow);    input [3:0] a;    input [3:0] b;    output [3:0] sum;    input sub;    output c1;    output overflow;      wire [3:0]invb;     assign invb = sub?~b:b;      rcl4bit rc4(a, invb, sub, sum, c1, overflow);  endmodule 

your overflow term doesn't make sense me, think overflow carry out, don't know why you've xor'd carry[2].

other that don't see wrong, don't see how giving 1100 output, , don't see why expect answer 0110 (6).

if 0100, , b 0011, invb 1100, plus cin means b you've got:

  0100   (a)   1100   (invb) + 0001   (cin) _________  10001   

overflow 1, , result 0001 (4-3 = 1).

have tried inspecting via waveform see results diverge this?


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